1. Field of the Invention
This invention relates to a static random access memory (SRAM) of a semiconductor memory constructed as an integrated circuit using insulated gate field effect transistors (IG-FET).
2. Description of the Prior Art
The SRAM including as the memory unit a flip-flop circuit using the IG-FET devices has been promoted in the high-speed operation and high integration, however, a signal delay due to resistance in the word-line of memory cells in an array has largely hindered its high-speed operation. The typical IG-FET SRAM at present is of polysilicon gate construction, which connects in common the gates of selecting transistors in the memory cells in the same row so as to form a word-line used for selecting the word direction of the memory cell array. The resistance of polysilicon used as the word-line is 20 to 30.OMEGA./.quadrature., more than 1000 times the value of metallic wirings, thereby creating a signal delay in the word-line, which is a rate limiting factor for the operation of memory.
In order to solve the above problem, one method proposed is that, instead of polysilicon, a low resistance wiring material, such as tungstosilicide be used. This results in the shortcoming that the manufacturing process must be changed following variation in the wiring material, and manufacturing cost becomes high in the manufacturing apparatus and materials.
Another method for solving the above problem is a divided word line (hereinafter referred to as DWL) method. The DWL method is disclosed in the Japanese Patent Publication No. Sho 59-49706 (1984) and also detailed in the "IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL. SC-18, No. 5", October, 1983. Next, concrete explanation will be given on this method.
FIG. 1 is a circuit diagram of a memory cell in the SRAM, in which two transistors (IG-FETs) Q.sub.1 and Q.sub.2 (both n-channel type) form a flip-flop, and connect with a power supply line PL between terminals 1 and 2 through load resistances R.sub.1 and R.sub.2. Transistors Q.sub.3 and Q.sub.4 (both n-channel type) are selecting transistors and are interposed between terminals 5 and 6 nodes of the transistors Q.sub.1 and Q.sub.2 with load resistances R.sub.1 and R.sub.2, and the gates thereof being connected to a word-line WL between terminals 3 and 4.
The power supply line PL and word-line WL connect with adjacent memory cells in the row direction, the power supply line PL concretely comprising a second layer of polysilicon, different from the word-line WL and generally forming the load resistance R.sub.1 and R.sub.2 due to high resistance at a part of the second layer. In a case where the load resistances R.sub.1 and R.sub.2 are constituted by the IG-FETs, the power supply line PL may be formed of a diffused layer on a substrate. The terminals 5 and 6 are connected to the adjacent memory cells to constitute the bit line. Generally low resistance metal, such as aluminum is used therefor, because the bit line needs to transmit a faint signal generated by the memory cell.
FIG. 2 is a circuit diagram of the SRAM carrying out the DWL method.
In this circuit, memory cells MC1, MC2 . . . MCn, and MCn+1 constructed as shown in FIG. 1 are disposed in array, and in FIG. 2, those in the same row are partially shown. The DWL method is characterized in that the memory cells in array are divided into blocks of plural rows. Reference numerals 21 and 22 designate the block selecting signal lines for selecting each divided block, which lines are connected to NOR circuits 24 and 25 provided at every row in the block respectively.
An inverter 26 comprising two FETs Q.sub.6 (p-channel type) and Q.sub.5 (n-channel type), forming a part of row selecting circuit, being connected in series with each other. Inverter 26 is connected between the power supply line PL and the grounding conductor and the output of the inverter 26 is connected as the common word line 27 to other input terminals of NOR circuits 24 and 25 of all the blocks in the same row (only two NOR circuits 24 and 25 are shown in FIG. 2, but actually the number of them corresponds to the number of blocks).
The power supply line PL is connected to the terminals 1 and 2 in common with all the blocks. The outputs of NOR circuits 24 and 25 are connected as the word lines to the terminals 3 and 4 at the memory cells in the same row of each block, and the bit lines 23, 23 . . . are connected to the terminals 5 and 6 being in common therewith in each row.
Next, explanation will be given on the operation of the circuit shown in FIG. 2. When both the common word line 27 of the outputs of the inverter 26 and the block selecting signal line 21 are at a level "0" and the block selecting signal line 22 is at a level "1", the output of NOR circuit 24 has a level "1", so that the memory cells MC1 and MC2 connected to the output of NOR circuit 24 are selected. Meanwhile, since the block selecting signal line 22 is at a level "1", the output of NOR circuit 25 goes to logical "0", so that memory cells MCn and MCn+1 connected to the word line of the output of the NOR circuit 25 are not selected.
The aforesaid DWL method, in which one circuit in each block is selectively connected to the common word line 27 (in FIG. 2, the NOR circuit 24 or 25), is characterized in that the load is small and the signal delay by the common word line 27 is reduced. Since the word line is divided per block, the DWL method is advantageous in that the word line is small in length, the wiring resistance is small, and the cell selecting transistors Q.sub.3 and Q.sub.4 to be loaded on the word line function with respect to the memory cells only in the block. Therefore, the load is 1/block in comparison with the conventional word line in common with the entire memory cell array. In brief, the DWL method is less in delay than the common word line and word line method so as to enable high-speed operation.
The DWL method has the aforesaid advantage, but needs the common word line 27 as shown in FIG. 2 in order to demonstrate such advantage.
Generally, this kind of semiconductor memory, such as the SRAM, is disposed on a chip in high density, whereby the wiring material of the common word line 27 cannot be in the same layer as the word line and the power supply line PL and cannot be in the same layer as the bit line 23. Hence, a new wiring layer, such as an aluminum wiring, needs to be provided at the second layer. Therefore, the SRAM has the shortcoming that the manufacturing process is complicated, the yield lower, and the manufacturing cost is high.